The present invention relates to a semiconductor memory device, and, more specifically, to a semiconductor memory device having a voltage converting circuit which receives an external power voltage and produces a internal power voltage different from the external power voltage.
As capacity of the semiconductor memory device is increased, each element formed therein is required to operate on a lower voltage. Accordingly, it is necessary to reduce a power source voltage to be supplied to each element in order to prevent the elements such as a MOS transistor from being destroyed. For example, in 64M-bits DRAM, it is required that the internal elements such as MOS transistors operates on 2.0 V.
For this purpose, such a technique is widely employed that the external power source voltage is reduced or lowered to produce an internal power source voltage having a level suitable for fine elements. Such a technique has materialized by a voltage reducing circuit. On the other hand, the semiconductor memory device has a plurality of memory cell arrays and the internal power source voltage is provided to every the memory cell array.
An apparatus satisfying the above conditions is suggested as follow. The apparatus has one voltage reducing circuit and a plurality of memory cell arrays commonly connected to the voltage reducing circuit. However, the wiring layer connected between the voltage reducing circuit and memory cell arrays must be long since the distance between the voltage reducing circuit and memory cell arrays becomes long. On the other hand, the wiring layer naturally have a sufficient width to provide a sufficient current to the plurality of memory cell arrays. That is why it is necessary to provide a large current to consume a lot of current in each memory cell array and to equally provide the current to the memory cell arrays. Accordingly, it is problem that a size of a semiconductor chip increases due to a large area of the wiring layer.
To solve the problem, Another apparatus is suggested. The apparatus has a plurality of voltage reducing circuit and a plurality of memory cell arrays each connected to the respective voltage reducing circuits. The length of the wiring layer can be short since the voltage reducing circuit is able to be arranged nearly with the respective memory cell arrays. The problem is therefore solve. However, New problem is occurred that the size of the semiconductor chip increases and the consumed current increases since a plurality of the voltage reducing circuits are needed.